1. Field of the Invention
The present invention relates to an error correction technique for data stored in a semiconductor memory.
2. Description of the Background Art
As recording media for a variety of data, nonvolatile semiconductor memories such as NAND flash memories and the like are widely used. With miniaturization of a process technology or the like, high integration of nonvolatile semiconductor memories is more and more progressing.
When data is written into a nonvolatile semiconductor memory, some errors occur in the written data in some cases. This is a so-called program disturb. Further, when data are repeatedly read out from a nonvolatile semiconductor memory, some errors also sometimes occur in stored data. This is a so-called read disturb. Therefore, for using nonvolatile semiconductor memories including NAND flash memories, it is indispensable to equip the memories with some error correction function.
As circuits for implementing the error correction function, ECC (Error Check and Correction) circuits are generally used. The ECC circuit calculates a syndrome from information data to be stored in a memory array. In the memory array, stored is code data in which the syndrome is added to the information data. The ECC circuit performs an error correction process on the code data read out from the memory array by using the syndrome.
In general, the level (high or low) of error correcting capability of the ECC circuit is in proportion to a syndrome length. As the error correcting capability increases, the syndrome length becomes larger and the code rate decreases. The decrease in the code rate results in a decrease in storage efficiency of the information data in a memory. Therefore, for determination of error correcting capability, it is necessary to consider both the error rate and the storage efficiency of the information data. The code rate refers to a ratio of a data length of the information data to a data length of the code data and has a close relation with the error correcting capability.
In nonvolatile semiconductor memories, time degradation of cells due to the miniaturization of the process technology is becoming pronounced. When a nonvolatile semiconductor memory continues to be used, the error rate increases as the cells are degraded. There is a possibility that the error correcting capability set in an initial state for use may become insufficient with time. Alternatively, when the error correcting capability is set higher from the beginning of use on the assumption that the cells become degraded with time, the storage efficiency of the information data unnecessarily decreases due to the decrease in the code rate.
National Publication of Translation No. 2010-518523 discloses a technique for changing the code rate and varying the error correcting capability in accordance with a change in the bit error rate.
In National Publication of Translation No. 2010-518523, the time degradation of a memory is dealt with by changing the code rate in accordance with a change in the bit error rate. Since the code rate is changed, however, the data management and operation becomes complicated. In other words, since the data length of the code data is changed, the data structure needs to be restructured or the like and the process becomes complicated.